t27c debug-hir on axi4.t27 -- five channels as IR

The AXI4 spec lowered to hardware IR: the five channels and their handshakes as the compiler structures them.

t27c debug-hir specs/fpga/axi4.t27

            value: "bits + 8",                                                                          
        },                                                                                              
        HirAssign {                                                                                     
            target: "bits",                                                                             
            value: "bits + 3",                                                                          
        },                                                                                              
        HirAssign {                                                                                     
            target: "bits",                                                                             
            value: "bits + 2",                                                                          
        },                                                                                              
        HirAssign {                                                                                     
            target: "bits",                                                                             
            value: "bits + 8",                                                                          
        },                                                                                              
    ],                                                                                                  
    always_blocks: [],                                                                                  
    instances: [],                                                                                      
    memories: [],                                                                                       
    clock_domains: [],                                                                                  
    clock_crossings: [],                                                                                
    fifos: [],                                                                                          
    bus_ports: [],                                                                                      
    apb_bridges: [],                                                                                    
    gf16_accels: [],                                                                                    
    formal_asserts: [],                                                                                 
    formal_covers: [],                                                                                  
    formal_assumes: [],                                                                                 
    formal_config: None,                                                                                
    ternary_cores: [],                                                                                  
}files $

recorded 2026-10-08 00:22 UTCreal 3.2 sshown 3.2 sexit codes 0

$ t27c debug-hir specs/fpga/axi4.t27

Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. Any silence longer than 2 s is shown for 2 s, and the title bar says so while it happens. Edited: home directory shown as ~.

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