Place and route to a loaded bitstream, timed

router1, bitwalk, xc7frames2bit, SRAM load: 19.06 s here, on a laptop at load average ~110.

Place and route to a loaded bitstream: the CLK_PERF2 probe, timed

  HCLK_L_X15Y234.ENABLE_BUFFER.HCLK_CK_BUFRCLK2                                                         
  HCLK_CMT_X8Y234.HCLK_CMT_CK_BUFRCLK2_USED                                                             
  HCLK_CMT_L_X256Y234.HCLK_CMT_CK_BUFRCLK2_USED                                                         
$ ~/t27-xilinx7/specs/xilinx7/bitwalk --fasm ~/.cache/x7/fasm/db-artix7-xc7a200tfbg484-2-db-new-v2.txt r
ec/r1.fasm rec/r1.frames                                                                                
rec/r1.frames: 20230 frames, 3848 bits, required 0, stepdown 96, ppip lines 370, outside the tile 0 (wra
pped below the frame 0, dropped above it 0), own bits outside the frame 0 (db 394.4 ms, total 933.5 ms) 
  rc=0  1.14 s                                                                                          
$ xc7frames2bit --part_file db-new/artix7/xc7a200tfbg484-2/part.yaml --part_name xc7a200tfbg484-2 --frm_
file rec/r1.frames --output_file rec/r1.bit                                                             
  rc=0  2.11 s                                                                                          
  past the sync word, rec/r1.bit == r1-new.bit (the build flashed on 2026-10-04)                        
$ openFPGALoader -c digilent_hs2 --freq 30000000 rec/r1.bit                                             
empty                                                                                                   
Jtag frequency : requested 30.00MHz   -> real 30.00MHz                                                  
Open file DONE                                                                                          
Parse file DONE                                                                                         
load program                                                                                            
Load SRAM: [==================================================] 100.00%                                 
Done                                                                                                    
Shift IR 35                                                                                             
ir: 1 isc_done 1 isc_ena 0 init 1 done 1                                                                
  rc=0  9.85 s                                                                                          

  place and route        5.95 s                                                                         
  FASM to frames         1.14 s                                                                         
  frames to bitstream    2.11 s                                                                         
  flash to SRAM          9.85 s                                                                         
  total                 19.06 s                                                                         
board $

recorded 2026-10-03 19:54 UTCreal 22.6 sshown 18.6 sexit codes 0

$ python3 perf2.py loop --out rec --flash

Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. Any silence longer than 2 s is shown for 2 s, and the title bar says so while it happens. Edited: home directory shown as ~.

Read the post GIF Preview card