Before: a full build before the board run

T27_SILICON_REBUILD=1 forces yosys, nextpnr and the bitstream for ternary_link: what an approved board run waited for before t27#8797.

t27 · before: a full build before the board run

t27 $ time T27_SILICON_REBUILD=1 tri hot prebuild specs/fpga/ternary_link.t27 --top fpga/verilog/ternary
_link_jtag.v --pnr-seed 11 | cut -c1-100
=== t27c silicon: specs/fpga/ternary_link.t27 on artix200t (xc7a200tfbg676-1) ===

  stage                          time      rc      artefact  note
  ------------------------------------------------------------------------------
  OK   spec -> Verilog          0.03s       0       12992 B  1 $display (T167: stripped below, not s
  OK   yosys                    3.50s       0     9486376 B  59 LUT, 8 CARRY4, 0 DSP48E1 | BSCANE2 x
  OK   datapath survives        0.00s       0             -  8 CARRY4 == floor, and the DUT ALONE ha
  OK   nextpnr @70.77MHz, Fmax   26.40s       0       92451 B  Max frequency for clock 'cfgmclk': 34
  OK   BSCAN chain == site      0.00s       0             -  JTAG_CHAIN(3) at BSCAN3 -- agree
  OK   fasm2frames              1.72s       0    22698060 B
  OK   frames -> bitstream      0.38s       0     9730824 B

  bitstream stored for reuse: ~/.cache/t27/bitstreams/e4b2e2db3fd4fd83fa62f4a86014d65002
PASS (build only) -- rerun without --skip-hardware to load and read.
real 32.377s
t27 $

recorded 2026-10-11 06:56 UTCreal 33.7 sshown 33.1 s

$ time T27_SILICON_REBUILD=1 tri hot prebuild specs/fpga/ternary_link.t27 --top fpga/verilog/ternary_link_jtag.v --pnr-seed 11 | cut -c1-100

Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. No silence was shortened. Edited: home directory shown as ~, temp directory shown as $TMPDIR.

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