tri hot prebuild: the bitstream from the reuse cache

The same inputs again: the bitstream comes from the reuse cache, and the cable is never touched.

t27 · after: tri hot prebuild, the bitstream from the reuse cache

t27 $ time tri hot prebuild specs/fpga/ternary_link.t27 --top fpga/verilog/ternary_link_jtag.v --pnr-see
d 11 | cut -c1-100
=== t27c silicon: specs/fpga/ternary_link.t27 on artix200t (xc7a200tfbg676-1) ===

  stage                          time      rc      artefact  note
  ------------------------------------------------------------------------------
  OK   spec -> Verilog          0.06s       0       12992 B  1 $display (T167: stripped below, not s
  OK   bitstream REUSED         0.00s       0     9730824 B  same inputs, same tools: ~/

PASS (build only) -- rerun without --skip-hardware to load and read.
real 0.497s
t27 $

recorded 2026-10-11 06:56 UTCreal 1.8 sshown 1.2 s

$ time tri hot prebuild specs/fpga/ternary_link.t27 --top fpga/verilog/ternary_link_jtag.v --pnr-seed 11 | cut -c1-100

Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. No silence was shortened. Edited: home directory shown as ~, temp directory shown as $TMPDIR.

GIF Preview card