Add it up on every clock
You will learn
What on_clock adds to the dot product, and why this spec's tests never reach the register.
stream_ternary_mac.t27 keeps the same dot27 and adds a register, acc, and on_clock, which adds dot27(a, b) to acc. on_clock is clocked: it runs once per clock edge, and acc holds its value between edges. In the generated Verilog, rst_n low clears acc and acc changes only while en is high; the spec itself has no en. The native t27c runs all 4 tests, all pass, none vacuous; the browser skips them for want of assert_eq. All 4 call dot27 and none drives on_clock, so the test-waves widget, not a test, checks the accumulate line. The recording narrows the mask for a on line 26 from 3 to 1, so a P in a reads as N, and exactly one test fails, dot_all_p_x_all_p. Every byte in the recording was printed by the command; only the typing is staged.
Try it
In the recording, find the mask that changes and the test that fails; then in the spec frame find on_clock and check that no test calls it.
t27c on the t27c lab (Railway), spec at t27 5ff0ec512: 4 tests pass natively; a lane mask that loses a bit fails exactly one test, dot_all_p_x_all_p; git restores the spec.
specs/ternary/stream_ternary_mac.t27
module StreamTernaryMac;
// #1764: a STREAMING ternary MAC -- the on-hardware BitNet inference primitive.
//
// Each clock cycle consumes one packed 27-trit (a, b) pair on input data ports
// and accumulates their dot product into a registered accumulator. This is a
// real datapath generated entirely from spec:
// input ports (a, b) -> ternary sign-multiply adder-tree (dot27)
// -> accumulate register (acc) -> output port (acc)
// It synthesizes to Artix-7 fabric (yosys synth_xilinx: the dot27 adder-tree in
// LUTs + a 32-bit accumulate register in FDCE + CARRY4), and `en` gates the
// accumulation so a caller can stream N vectors then read the running sum.
//
// The dot27 / tmul / tp primitives are the bit-exact-verified ones from
// ternary_mac.t27 (#1743, cross-checked vs an independent reference on 300
// random vectors). The only new piece is the `on_clock` streaming wrapper.
// Sign-only ternary multiply of two packed trits {N=0b00, Z=0b01, P=0b10}.
fn tmul(ta: u8, tb: u8) -> i8 {
if (ta == 1) { return 0; }
if (tb == 1) { return 0; }
if (ta == tb) { return 1; }
return -1;
}
// One trit position i of two 54-bit packed vectors (trit i at [2i+1:2i]).
fn tp(a: u64, b: u64, i: u32) -> i8 {
return tmul(((a >> (i << 1)) & 3) as u8, ((b >> (i << 1)) & 3) as u8);
}
// 27-trit ternary dot product, loop-free. Result in [-27, +27].
fn dot27(a: u64, b: u64) -> i8 {
return tp(a,b,0) + tp(a,b,1) + tp(a,b,2) + tp(a,b,3) + tp(a,b,4)
+ tp(a,b,5) + tp(a,b,6) + tp(a,b,7) + tp(a,b,8) + tp(a,b,9)
+ tp(a,b,10) + tp(a,b,11) + tp(a,b,12) + tp(a,b,13) + tp(a,b,14)
+ tp(a,b,15) + tp(a,b,16) + tp(a,b,17) + tp(a,b,18) + tp(a,b,19)
+ tp(a,b,20) + tp(a,b,21) + tp(a,b,22) + tp(a,b,23) + tp(a,b,24)
+ tp(a,b,25) + tp(a,b,26);
}
// Registered accumulator, exposed as an output data port. i32 so it never
// overflows across a realistic stream (each step adds a value in [-27, +27]).
var acc : i32 = 0
// The clocked process: `a` and `b` are streaming input data ports; each cycle
// (while `en`) the dot product of the current pair is added to `acc`.
fn on_clock(a: u64, b: u64) {
acc = acc + (dot27(a, b) as i32)
}
test dot_all_n_x_all_n { assert_eq(dot27(0, 0), 27); }
test dot_all_n_x_all_p { assert_eq(dot27(0, 12009599006321322), -27); }
test dot_all_p_x_all_p { assert_eq(dot27(12009599006321322, 12009599006321322), 27); }
test dot_all_z { assert_eq(dot27(6004799503160661, 6004799503160661), 0); }
endmodule
All lessons
Module 1 · Lab: our own research
A number format of our own, an honest scoreboard, and a model's tables multiplied on the board.
Module 2 · AI numbers: the MX block
How AI chips keep weights in a few bits: one shared scale per block, the scale byte itself, and what one outlier does to its neighbours.
Module 3 · Ternary weights
Weights that are only minus, zero or plus a scale, the five rules a ternary alphabet must pass, and a test pass that checked nothing.
Module 4 · The Ternary Network Float
A rule the compiler enforces before any test runs, and a 17-bit float whose exponent is four balanced trits.
Module 5 · Arithmetic on signed numbers
Multiply two signed numbers, add them when their signs differ, and do both at once in a multiply-accumulate.
Module 6 · Parts of a neuron
A ReLU that bends at zero, a power of two for softmax, and an argmax that names the answer.
Module 7 · Learning from a mistake
A loss that prices a wrong guess in bits, one step that moves a weight against its gradient, and the hidden layer that XOR needs.
Module 8 · BitNet: ternary networks
A threshold that squeezes a sum back to three values, one neuron that becomes a different function when its weights change, and a neuron that reads its inputs 27 trits at a time.
Module 9 · The ternary MAC as a chip
The 27-trit dot product as wires with no register, the same sum added into a register on every clock, and a small whole network to close the course.